High- Level Synthesis Using SPARK and Systolic Array. Recently, SPARK parallelizing high- level synthesis software tool has been developed. It takes a behavioral ANSI- C code as an input, schedules it using speculative code motions and loop transformations, generates a finite state machine for the scheduled design graph, and then finally outputs a synthesizable RTL VHDL code. To handle loop algorithm, SPARK employs various loop transformations such as loop invariant code motion, loop unrolling, loop index variable elimination and loop shifting. In loop synthesis, however, SPARK does not produce circuit description whose quality can compete with manual designs. With the objective of improving the quality of high- level synthesis results for designs with loops, this paper shows an upgrade of SPARK through transforming nested loops into a 2- D systolic array to increase parallelism. The C- to- VHDL loop synthesis in this paper achieves synthesis results that are better than those achieved from a current version of SPARK for matrix- matrix multiplication and FIR filter, and can be incorporated into SPARK parallelizing high- level synthesis framework. Download SPARK Parallelizing High- Level Synthesis Tool. This software is Copyright 2. The Regents of the University of California. The software program and documentation are supplied. The Regents does not. Download at your own risk ! Furthermore, the. University of California does not warrant that the operation of the. The end- user understands. The University of California. The software provided hereunder is on an . An overview of today’s high-level synthesis tools. High-level synthesis improves design productivity by automating the re. As can be seen on the Y-chart (Fig. An Introduction to High-Level Synthesis Philippe Coussy. High-level synthesis raises the design abstraction level and allows rapid gener-.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. Archives
December 2016
Categories |